At this point of time, no current will flow from the junction field effect transistor. Thus, the Pinch-off voltage can be defined as the reverse voltage applied at the gate to source terminal such that the drain current will cease completely. This point of voltage is called pinch-off voltage. Thus, at a certain point of negative voltage, a point will reach when the drain current completely cuts off, and the depletion layer from both the sides will almost touch each other at region nearer to drain terminal. The reversed biased PN junction will create the depletion region and more the reverse voltage more will be the width of the depletion region. This forms the reverse biased PN junction. The negative voltage at gate terminal implies that the P-terminal is connected to negative terminal of battery while N terminal is connected to the positive terminal. When the Large negative bias is applied: When the large negative gate to source voltage is applied, then this large negative electric field will contribute to increment of the width of the depletion region.Besides, the current flowing from drain to source flows from the region of high resistance to low resistance, thus the voltage drop will be created.

This is because the gate is more negative at the points which are nearer to drain than to source. The width of the depletion region is more near the drain terminal and less near the source terminal. This is because as the width of the depletion layer increases the space provided for electrons to flow from source to drain will decrease and eventually the drain current decreases. The wedge shape depletion layer so formed will reduce the magnitude of the current through the N-channel. Due to this the width of the depletion region is more in N-Channel than in P-channel. The N-channel is moderately doped while P-channel is highly doped. Simultaneously, the positive voltage is applied to the drain to the source terminal. when the gate to source voltage is negative, then the width of depletion region starts increasing. When small negative bias is applied: When a small negative voltage is applied to the gate terminal i.e.The ohmic contacts are made at drain, gate and source to provide the connection. Thus, current will flow from drain to source terminal. The direction of flow of current is opposite to the direction of flow of electron. The electrons will flow from source terminal to gate terminal. In this case, the width of depletion region will remain constant. Besides, the voltage at drain terminal is also 0. It means the gate to source voltage (Vgs) in this case is 0. When NO bias is applied: In this case, no bias is applied to the gate terminal.Its working can be easily understood with the help of three cases. The N-channel involves the conduction due to the flow of electrons while the P-channel JFET involves conduction due to holes. The difference between these two JFETs is the current carriers involved in the conduction mechanism. To understand the working characteristics of JFET we need to consider one type of JFET either N-channel JFET or P-channel JFET.

Therefore, the output current is termed as the drain current. The output current flows from the drain terminal towards the source terminal.

Jfet transistor diagram